Electrodes for semiconductor devices and methods of forming the same

ABSTRACT

A III-N semiconductor HEMT device includes an electrode-defining layer on a III-N material structure. The electrode-defining layer has a recess with a first sidewall proximal to the drain and a second sidewall proximal to the source, each sidewall comprising a plurality of steps. A portion of the recess distal from the III-N material structure has a larger width than a portion of the recess proximal to the III-N material structure. An electrode is in the recess, the electrode including an extending portion over the first sidewall. A portion of the electrode-defining layer is between the extending portion and the III-N material structure. The first sidewall forms a first effective angle relative to the surface of the III-N material structure and the second sidewall forms a second effective angle relative to the surface of the III-N material structure, the second effective angle being larger than the first effective angle.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a continuation of U.S. application Ser. No. 14/179,788, filed on Feb. 13, 2014, which claims priority to U.S. Provisional Application No. 61/765,635, filed on Feb. 15, 2013. The disclosures of the prior applications are considered part of and are incorporated by reference in the disclosure of this application.

TECHNICAL FIELD

This invention relates to semiconductor electronic devices, specifically devices with electrodes connected to field plates.

BACKGROUND

To date, modern power semiconductor diodes such as high-voltage P-I-N diodes, as well as power transistors such as power MOSFETs and Insulated Gate Bipolar Transistors (IGBT), have been typically fabricated with silicon (Si) semiconductor materials. More recently, silicon carbide (SiC) power devices have been researched due to their superior properties. III-Nitride (III-N) semiconductor devices are now emerging as an attractive candidate to carry large currents and support high voltages, and provide very low on resistance, high voltage device operation, and fast switching times. As used herein, the terms III-N or III-Nitride materials, layers, devices, etc., refer to a material or device comprised of a compound semiconductor material according to the stoichiometric formula B_(w)Al_(x)In_(y)Ga_(z)N, where w+x+y+z is about 1.

An example of a III-N high electron mobility transistors (HEMT) of the prior art is shown in FIGS. 1 and 2. The III-N HEMT of FIG. 1 includes a substrate 10, a III-N channel layer 11, such as a layer of GaN, atop the substrate, and a III-N barrier layer 12, such as a layer of Al_(x)Ga_(1-x)N, atop the channel layer. A two-dimensional electron gas (2DEG) channel 19 is induced in the channel layer 11 near the interface between the channel layer 11 and the barrier layer 12. Source and drain contacts 14 and 15, respectively, form ohmic contacts to the 2DEG channel. Gate contact 16 modulates the portion of the 2DEG in the gate region, i.e., directly beneath gate contact 16.

Field plates are commonly used in III-N devices to shape the electric field in the high-field region of the device in such a way that reduces the peak electric field and increases the device breakdown voltage, thereby allowing for higher voltage operation. An example of a field plated III-N HEMT of the prior art is shown in FIG. 2. In addition to the layers included in the device of FIG. 1, the device in FIG. 2 includes a field plate 18 which is connected to gate 16, and an insulator layer 13, such as a layer of SiN, is between the field plate 18 and the III-N barrier layer 12. Field plate 18 can include or be formed of the same material as gate 16. Insulator layer 13 can act as a surface passivation layer, preventing or suppressing voltage fluctuations at the surface of the III-N material adjacent to insulator layer 13.

Slant field plates have been shown to be particularly effective in reducing the peak electric field and increasing the breakdown voltage in III-N devices. A prior art III-N device similar to that of FIG. 2, but with a slant field plate 24, is shown in FIG. 3. In this device, gate 16 (i.e., the portion of electrode 29 that is between the vertical dashed lines) and slant field plate 24 are formed of a single electrode 29. Insulator layer 23, which can be SiN, is an electrode-defining layer that contains a recess which defines at least in part the shape of electrode 29. Electrode-defining layer 23 can also act as a surface passivation layer, preventing or suppressing voltage fluctuations at the surface of the III-N material adjacent to electrode-defining layer 23. The gate 16 and slant field plate 24 in this device can be formed by first depositing electrode-defining layer 23 over the entire surface of III-N barrier layer 12, then etching a recess through the electrode-defining layer 23 in the region containing gate 16, the recess including a slanted sidewall 25, and finally depositing electrode 29 at least in the recess and over the slanted sidewall 25.

Slant field plates, such as field plate 24 in FIG. 3, tend to spread the electric fields in the device over a larger volume as compared to conventional field plates, such as field plate 18 in FIG. 3, which do not include a slanted portion. Hence, slant field plates tend to be more effective at reducing the peak electric field in the underlying device, thereby allowing for larger operating and breakdown voltages.

When the device of FIG. 3 is biased in the off state with a large voltage applied to the drain 15 relative to the source 14, the electric field in the semiconductor layers 11 and 12 is spread over the horizontal length of the field plate 24. As such, for a given thickness of the electrode-defining layer 23, the horizontal length of the region which the electric field is spread over, is largely determined by the angle 26 which the field plate forms with the surface 28 of the underlying III-N material structure. A smaller angle 26 results in a greater spreading of the electric fields, allowing for correspondingly larger operating and breakdown voltages of the device. For example, in a III-N device with an electrode-defining layer 23 which is about 0.85 microns thick, an angle of about 40 degrees or less may be required for reliable 50V or 100V operation, whereas an angle of about 10 degrees or less may be required for reliable 300V or 600V operation. However, decreasing the angle 26 results in a longer lateral extension of the field plate 24 towards the drain 15, which can necessitate a larger spacing between the gate 16 and drain 15. Furthermore, it can be difficult to reproducibly fabricate slant field plates 24 with such small angles 26. Field plate structures that can provide adequate suppression of peak electric fields and can be fabricated reproducibly are desirable.

SUMMARY

In a first aspect, a III-N transistor is described. The transistor includes a III-N material structure, a source and a drain, and an electrode-defining layer having a thickness. The electrode-defining layer is over a surface of the III-N material structure and includes a recess with a first sidewall proximal to the drain and a second sidewall proximal to the source, where the first and second sidewalls each comprise a plurality of steps. A portion of the recess distal from the III-N material structure has a first width, and a portion of the recess proximal to the III-N material structure has a second width, with the first width being larger than the second width. The transistor further includes an electrode in the recess, the electrode including an extending portion at least partially over the first sidewall. The first sidewall forms a first effective angle relative to the surface of the III-N material structure and the second sidewall forms a second effective angle relative to the surface of the III-N material structure, the second effective angle being larger than the first effective angle.

In a second aspect, a transistor is described. The transistor includes a semiconductor material structure including a channel therein, a source and a drain each in electrical contact with the channel, and an electrode between the source and the drain. The electrode includes a gate and an extending portion, with the extending portion extending from the gate towards the drain. The transistor has a gate-drain spacing of less than 20 microns, an off-state drain current per unit gate width of the transistor is about 10⁻⁸ Amps/mm or less while the gate is biased below a threshold voltage of the transistor relative to the source and a drain-source voltage of the transistor is about 600V or larger, and a dynamic on-resistance of the transistor when the transistor is switched on with a switching time of 2 microseconds or less is less than 1.1 times a DC on-resistance of the transistor.

In a third aspect, a transistor is described. The transistor includes a semiconductor material structure including a channel therein, a source and a drain each in electrical contact with the channel, and an electrode between the source and the drain. The electrode includes a gate and an extending portion, with the extending portion extending from the gate towards the drain. The transistor has a gate-drain spacing of less than 20 microns, the extending portion includes a plurality of steps, wherein the number of steps in the plurality of steps per micron of length of the extending portion is greater than 0.4, and an off-state drain current per unit gate width of the transistor is about 10⁻⁸ Amps/mm or less while the gate is biased below a threshold voltage of the transistor relative to the source and a drain-source voltage of the transistor is about 600V or larger.

In a fourth aspect, a method of forming a semiconductor device is described. The method includes providing a semiconductor material structure, forming an electrode-defining layer having a thickness on a surface of the semiconductor material structure, and patterning a masking layer over the electrode-defining layer, the masking layer including an opening having a width. The method further includes etching the electrode-defining layer to form a recess therein, the recess having a first sidewall and a second sidewall opposite the first sidewall, the first and second sidewalls each comprising a plurality of steps, where the first sidewall forms a first effective angle relative to the surface of the semiconductor material structure and the second sidewall forms a second effective angle relative to the surface of the semiconductor material structure, and a portion of the recess distal from the semiconductor material structure has a first width and a portion of the recess proximal to the semiconductor material structure has a second width, the first width being larger than the second width. The etching of the electrode-defining layer includes performing a first procedure and a second procedure, the first procedure comprising removing a portion of the electrode-defining layer, and the second procedure comprising removing a portion of the masking layer without entirely removing the masking layer, where the second procedure causes an increase in the width of the opening in the masking layer. Furthermore, the etching of the electrode-defining layer results in the second effective angle being larger than the first effective angle.

In a fifth aspect, a method of forming a semiconductor device is described. The method includes providing a semiconductor material structure, forming an electrode-defining layer having a thickness on a surface of the semiconductor material structure, and patterning a masking layer over the electrode-defining layer, the masking layer including an opening. The opening forms a pattern including a plurality of regions having a first width interlaced with a plurality of regions having a second width, the first width being larger than the second width. The method further includes etching the electrode-defining layer beneath the opening to form a recess therein, the recess having a first sidewall and a second sidewall, the first sidewall including a plurality of sections each adjacent to one of the regions having the first width, and the second sidewall including a plurality of sections each adjacent to one of the regions having the second width. Additionally, the etching results in an average slope of the sections of the second sidewall being larger than an average slope of the sections of the first sidewall.

Each of the devices and methods described herein can include one or more of the following features or steps. The second effective angle can be substantially larger than the first effective angle. The second effective angle can be at least 10 degrees larger than the first effective angle. The semiconductor or III-N material structure can include a first III-N material layer, a second III-N material layer, and a 2DEG channel induced in the first III-N material layer adjacent to the second III-N material layer as a result of a compositional difference between the first III-N material layer and the second III-N material layer. The first III-N material layer can include GaN and the second III-N material layer can include AlGaN, AlInN, AlInGaN, or BAlInGaN. The first III-N material layer and the second III-N material layer can be group III-face or [0 0 0 1] oriented or group-III terminated semipolar layers, and the second III-N material layer can be between the first III-N material layer and the electrode-defining layer. The first III-N material layer and the second III-N material layer can be N-face or [0 0 0 −1] oriented or nitrogen-terminated semipolar layers, and the first III-N material layer can be between the second III-N material layer and the electrode-defining layer. The recess can extend through the entire thickness of the electrode-defining layer. The recess can extend into the III-N material structure and/or through the 2DEG channel.

The electrode-defining layer can comprise SiN_(x). A thickness of the electrode-defining layer can be between about 0.1 microns and 5 microns. The transistor can further comprise a dielectric passivation layer between the III-N material structure and the electrode-defining layer, the dielectric passivation layer directly contacting a surface of the III-N material adjacent to the electrode. The dielectric passivation layer can comprise SiN_(x). The dielectric passivation layer can be between the electrode and the III-N material structure, such that the electrode does not directly contact the III-N material structure. The transistor can further include an additional insulating layer between the dielectric passivation layer and the electrode-defining layer. The additional insulating layer can comprise AlN. The extending portion of the electrode can directly contact the sidewall.

The electrode can include a gate in a gate region of the transistor, and the plurality of steps in the first and second sidewalls can each include a first step having a first step width directly adjacent to the gate, a second step having a second step width directly adjacent to the first step, and a third step having a third step width directly adjacent to the second step, wherein a ratio of the first step width to the second step width in the plurality of steps in the first sidewall is substantially the same as a ratio of the first step width to the second step width in the plurality of steps in the second sidewall. A ratio of the first step width to the third step width in the plurality of steps in the first sidewall can be substantially the same as a ratio of the first step width to the third step width in the plurality of steps in the second sidewall. A sum of the first step width, the second step width, and the third step width in the first sidewall can be greater than a sum of the first step width, the second step width, and the third step width in the second sidewall.

The semiconductor material structure can include a III-N material, and the channel can be in the III-N material. The DC on resistance of the transistor or device can be less than 12 ohm-millimeters. The field plate or the extending portion can have a length of 12 microns or less.

The etching can result in the second effective angle being substantially larger than the first effective angle. The etching can result in the second effective angle being at least 10 degrees larger than the first effective angle. The masking layer can comprise photoresist. The method can further comprise causing a redistribution of the photoresist in the masking layer prior to performing the etching step. Causing the redistribution of the photoresist can comprise thermally annealing the photoresist. The redistribution of the photoresist can result in the masking layer having a first slanted sidewall on one side of the opening and a second slanted sidewall on the opposite side of the opening. The redistribution of the photoresist can result in the second slanted sidewall having a greater slope than the first slanted sidewall. The method can further include removing the masking layer and forming an electrode in the recess. The etching can further include performing the first procedure a second time after the second procedure has been performed, and performing the second procedure a second time after the first procedure has been performed a second time. The etching can result in the recess extending through the entire thickness of the electrode-defining layer. The semiconductor material structure can comprise a III-N layer. The etching can comprise etching through the entire thickness of the electrode-defining layer and using the masking layer as an etch mask during the entirety of the etching. The etching can further comprise etching into a layer that is directly beneath the electrode-defining layer.

III-N devices which can be fabricated reproducibly, can support high voltages with low leakage, and at the same time can exhibit low on-resistance and high breakdown voltage, are described. Methods of forming the devices are also described. The III-N devices described herein can be transistors, and can be high-voltage devices suitable for high voltage applications. The details of one or more implementations of the invention are set forth in the accompanying drawings and description below. Other features and advantages of the invention will be apparent from the description and drawings, and from the claims.

DESCRIPTION OF DRAWINGS

FIGS. 1-3 are cross-sectional views of III-N HEMT devices of the prior art.

FIGS. 4-5 are cross-sectional views of implementations of III-N HEMT devices.

FIG. 6 is a plan view of the III-N HEMTs of FIGS. 4 and 5.

FIGS. 7-17 illustrate a method of forming the III-N HEMT of FIG. 4.

FIG. 18 is a cross-sectional view of another implementation of a III-N HEMT device.

Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION

Transistors based on III-N heterostructures are described. An electrode of the device is designed such that the device can be fabricated reproducibly, can support high voltages with low leakage, and at the same time can exhibit low on-resistance and low gate capacitance. Methods of forming the electrode are also described. The III-N devices described herein can be high-voltage devices suitable for high voltage applications. In such a high-voltage transistor, when the transistor is biased off (i.e., the voltage on the gate relative to the source is less than the transistor threshold voltage), it is at least capable of supporting all source-drain voltages less than or equal to the high-voltage in the application in which it is used, which for example may be 100V, 300V, 600V, 1200V, 1700V, or higher. When the high voltage transistor is biased on (i.e., the voltage on the gate relative to the source is greater than the transistor threshold voltage), it is able to conduct substantial current with a low on-voltage. The maximum allowable on-voltage is the maximum voltage that can be sustained in the application in which the transistor is used.

The transistors described herein each include a field plate structure which allows for comparable device operating and breakdown voltages to the device of FIG. 3, but which can be fabricated reproducibly. Additionally, the field plate configuration allows for a transistor designed for a given operating voltage to have a very small spacing between the gate and drain, in order to reduce the device on-resistance and minimize electrical losses.

The device described herein is illustrated in FIGS. 4-5 and 17-18. III-N transistors described herein each include an electrode-defining layer on top of a III-N material structure. The electrode-defining layer includes a recess, and an electrode is in the recess. The width at the top of the recess is greater than the width at the bottom of the recess. The electrode includes first and second extending portions on opposite sides of the electrode which are over portions of the electrode-defining layer. The first extending portion, which extends towards the drain electrode, functions as a field plate. The second extending portion extends towards the source electrode. The electrode is deposited conformally in the recess in the electrode-defining region with the extending portions over sidewalls of the recess. Hence, the profiles of the extending portions are at least partially determined by the profiles of the corresponding sidewalls. The sidewalls of the recess underneath the extending portions of the electrode include a plurality of steps. The sidewalls each form an effective angle relative to the uppermost surface of the underlying III-N material structure. The effective angle of the sidewall underneath the first extending portion, which defines (and is therefore the same as) the effective angle of the field plate, can be small enough to allow for high voltage operation of the device, as required by the circuit application in which the device is used. The effective angle of the sidewall underneath the second extending portion, which defines (and is therefore the same as) the effective angle of the second extending portion, is greater than the effective angle of the first extending portion. As compared to a device in which the first and second extending portions have substantially the same effective angle, this allows for a smaller gate-source capacitance for a given horizontal spacing between the source and the gate.

Referring to FIG. 4, a III-N HEMT includes a substrate 10 (although the substrate is optional), a first III-N layer 11 on top of the substrate, and a second III-N layer 12 on top of the first III-N layer. III-N layers 11 and 12 have different compositions from one another, the compositions selected such that a two-dimensional electron gas (2DEG) 19 (illustrated by a dashed line), i.e., a conductive channel, is induced in the first III-N layer 11 near the interface between the first and second III-N layers 11 and 12, respectively. An electrode-defining layer 33 is formed over the second III-N layer, the electrode-defining layer 33 including a recess 17 which can extend through the entire thickness of the electrode-defining layer 33. Alternatively, the recess 17 may only extend partially through the electrode-defining layer (not shown). The electrode-defining layer 33 is typically between about 0.1 microns and 5 microns thick, such as about 0.85 microns thick. The electrode-defining layer 33 can have a composition that is substantially uniform throughout. The electrode-defining layer 33 is formed of an insulator, such as silicon nitride (SiN_(x)).

A gate electrode 59 is formed in the recess. In the implementation shown in FIG. 4, the gate electrode 59 conformally covers the entire exposed surface in the recess, although in some implementations the gate electrode 59 only covers a portion of the exposed surface in the recess (not shown), as further described below. The portion 61 of gate electrode 59 in gate region 51 is the gate 61 of the device. Gate electrode 59 further includes a first extending portion 54, which is over at least a portion of the electrode-defining layer in the drain access region 53, and a second extending portion 55, which is over at least a portion of the electrode-defining layer in the source access region 52. The first extending portion 54 functions as a field plate, reducing the peak electric field in the device when the device is biased in the off state (i.e., with the gate-source voltage lower than the device threshold voltage) with a large drain-source voltage. The second extending portion 55 is included to ensure that the gate electrode 59 extends towards the source contact 14 at least beyond the source-side edge of the gate region 51 in case of misalignment of the gate electrode 59 to the recess during device fabrication. The gate electrode 59 is deposited conformally in the recess in the electrode-defining region.

The first extending portion 54 is over sidewall 43 of the recess, the sidewall 43 extending from point 44 (i.e., the portion of the electrode-defining layer 33 which is closest to gate region 51) all the way to the point 45 at the edge at the top of the recess which is closest to the drain. The second extending portion 55 is over sidewall 46 of the recess, the sidewall 46 extending from point 47 (i.e., the portion of the electrode-defining layer 33 which is closest to region 51) all the way to the point 48 at the edge at the top of the recess which is closest to the source. Hence, the profiles of the extending portions 54 and 55 are at least partially determined by the profiles of the sidewalls 43 and 46, respectively. Although the second extending portion 55 is shown to extend over the entire sidewall 46 at least to point 48, in some implementations extending portion 55 only extends part way up sidewall 46 (not shown). Having the second extending portion 55 only extend part way up sidewall 46 can decrease the gate capacitance, which improves the device performance. However, in some cases, having the second extending portion 55 extend over the entire sidewall 46 at least to point 48 reduces dispersion in comparison to a similar device in which the second extending portion 55 only extends part way up sidewall 46.

Source and drain contacts 14 and 15, respectively, are on opposite sides of the gate 59 and form ohmic contacts to the 2DEG channel 19. The III-N HEMT also includes a gate region 51, in which the gate 61 is deposited, and source and drain access regions 52 and 53, respectively, on opposite sides of the gate region. The regions 56 of the device structure in which the source and drain contacts 14 and 15, respectively, are deposited are referred to as the device ohmic regions. The source access region 52 is between the source contact 14 and gate 61 (i.e., the portion of gate electrode 59 that is in the gate region 51), and the drain access region 53 is between the drain contact 15 and gate 61. The III-N HEMT may also include additional III-N layers (not shown), for example a III-N buffer layer between the first III-N layer 11 and the substrate 10, or a III-N layer such as AIN between the first III-N layer 11 and the second III-N layer 12. The III-N HEMT can also optionally include a passivation layer 22 which contacts the III-N material surface at least in the access regions, and an additional dielectric layer 21 (also optional) between the passivation layer 22 and the electrode-defining layer 33. As shown in FIG. 4, the recess 17 in the electrode-defining layer 33 can extend through the entire thickness of the additional dielectric layer 21 but not through the passivation layer 22. Hence, passivation layer 22 can be between the III-N materials and gate 61 in the gate region 51, thereby serving as a gate insulator. A gate insulator can help prevent gate leakage currents in the HEMT.

Dispersion refers to a difference in observed current-voltage (I-V) characteristics when the device is operated under RF or switching conditions, as compared to when the device is operated under DC conditions. In III-N devices, effects such as dispersion are often caused by voltage fluctuations at the uppermost surface(s) of the III-N material layers, the result of charging of surface states during device operation. Accordingly, a passivation layer such as layer 22 in FIG. 4 prevents or suppresses dispersion by preventing or suppressing voltage fluctuations at the uppermost III-N surface.

In implementations where passivation layer 22 is included, electrode-defining layer 33 in combination with passivation layer 22 maintains effective passivation of the uppermost III-N surface of the device. When an additional dielectric layer 21, such as AlN, is included between the passivation layer 22 and electrode-defining layer 33, the additional dielectric layer 21 may need to be made thin enough, such as thinner than about 20 nm, thinner than about 10 nm, or thinner than about 5 nm, to ensure that effective passivation of the uppermost III-N surface is still maintained. Too thick an additional dielectric layer 21, such as greater than about 20 nm, can degrade the passivation effects of layers 22 and 33.

The III-N HEMT of FIG. 4 can be an enhancement-mode (i.e., normally off, with a threshold voltage greater than 0V) or a depletion-mode (i.e., normally on, with a threshold voltage less than 0V) device. Other configurations for the III-N HEMT of FIG. 4 are also possible. For example, in one implementation, the recess 17 in the electrode-defining layer 33 only extends partially through the thickness of the electrode-defining layer 33, such that a portion of the electrode-defining layer 33 is between the III-N materials and gate 61 in the gate region (not shown). In this case, electrode-defining layer 33 can also function as a gate insulator, and it may be possible to omit the passivation layer 22 and/or the additional dielectric layer 21. In another implementation, the recess 17 in the electrode-defining layer 33 additionally extends through the entire thickness of the passivation layer 22, and the gate 61 directly contacts the underlying III-N material (not shown). In yet another implementation, the recess 17 further extends into the III-N materials, as shown in FIG. 5.

FIG. 5 illustrates a III-N HEMT which is similar to that of FIG. 4, except that prior to deposition of gate electrode 59, the recess 17 in the electrode-defining layer 33 is further etched to extend through the passivation layer 22 and into the III-N material structure (layers 11 and 12). As shown in FIG. 5, the recess 17 can extend through the 2DEG 19. In the case where the recess 17 extends through the 2DEG 19, the HEMT may be an enhancement-mode device.

Referring to FIGS. 4 and 5, sidewalls 43 and 46 of the electrode-defining layer 33 each include a plurality of steps (and hence the extending portions 54 and 55 of the gate electrode 59 also each include a plurality of steps). The sidewalls 43 and 46 each have an effective slope, which is equal to the slope of the dashed lines 63 and 66, respectively, where dashed line 63 passes through points 44 and 45, and dashed line 66 passes through points 47 and 48. As such, the sidewalls 43 and 46 each form an effective angle 36 and 37, respectively, with the uppermost surface of the underlying III-N material structure. Or stated differently, each of sidewalls 43 and 46 have an effective slope, the effective slope being equal to the slope of dashed line 63 and 66, respectively.

As shown in FIGS. 4 and 5, the effective slope of sidewall 46 is greater than, and in many cases substantially greater than, the effective slope of sidewall 43. Correspondingly, the effective angle 37 formed by sidewall 46 relative to the uppermost surface of the III-N material structure is larger, for example substantially larger or at least 10 degrees larger, than the effective angle 36 formed by sidewall 43 relative to the uppermost surface of the III-N material structure. The effective angle 36 of the sidewall 43 that is adjacent to the drain 15 is maintained sufficiently small to allow for larger off-state voltages to be applied without the device suffering from high-field breakdown or other deleterious effects associated with large electric fields in the device. That is, increasing effective angle 36 typically results in an increase in the peak electric field in the device for a given drain-source voltage when the device is in the off state (i.e., when the gate is biased relative to the source at a voltage which is less than the device threshold voltage), leading to lower off-state operating and breakdown voltages. However, for a given separation between the source 14 and gate 61, increasing the effective angle 37 of sidewall 46 can reduce the gate-source capacitance, which can be beneficial for device performance. If the effective angle 37 were made to be substantially the same as angle 36, rather than being greater than angle 37 as shown, the separation between the source 14 and the gate 61 may need to be increased to allow for reliable device fabrication and to prevent the gate-source capacitance from being too large.

FIG. 6 is a plan view (top view) of the devices of FIGS. 4 and 5, and includes alternating “fingers” of source contact 14 and drain contact 15, with the source contacts 14 connected to a source contact pad 64 and the drain contacts 15 connected to a drain contact pad 65. Dashed line 60 indicates the slice corresponding to the cross sections illustrated in FIGS. 4 and 5. As shown in FIG. 6, the gate 61 is formed in a serpentine-like pattern with regions of width S1 interlaced with regions of width D1, where D1 is substantially larger than S1. The fingers of source contact 14 are in the regions of width S1, and the fingers of drain contact 15 are in the regions of width D1. The gate 61 may also be connected to a gate contact pad (not shown). Although FIG. 6 illustrates 3 source fingers and 3 drain fingers, in general the device can include fewer or more source and drain fingers.

Forming the recess 17 containing the gate electrode 59 in the shapes illustrated in FIGS. 4 and 5, where each of sidewalls 43 and 46 include a plurality of steps and have a different effective slope can be difficult to achieve reproducibly using conventional techniques. A simple and reproducible method of fabricating the devices of FIGS. 4-6 is illustrated in FIGS. 7-16. The method utilizes the difference in widths S1 and D1, described above with reference to FIG. 6, in order to achieve a recess 17 in the electrode-defining layer 33 having the profile shown in FIGS. 4 and 5, where the effective slope of sidewall 46 is greater than the effective slope of sidewall 43. The method only requires a single lithography step yet still achieves a profile for recess 17 in which the effective slope of sidewall 46 is greater (e.g., substantially greater) than the effective slope of sidewall 43. Other processes that can be used to achieve such a profile typically involve multiple lithography steps and are therefore more complicated and expensive than the method illustrated in FIGS. 7-16 and described below.

Referring to FIG. 7, III-N material layers 11 and 12 are formed on substrate 10, for example by metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). Passivation layer 22, formed over the III-N material layers 11 and 12, is then deposited by methods such as MOCVD or plasma enhanced chemical vapor deposition (PECVD). Next, as seen in FIG. 8A, source and drain contacts 14 and 15, respectively, are formed. The source and drain contacts are in electrical contact with the 2DEG 19 induced in the III-N material layers. Source and drain contacts 14 and 15, respectively, can be formed in a number of ways. For example, a metal or combination of metals can be deposited, for example by evaporation, sputtering, or CVD, in ohmic contact regions 56 (shown in FIG. 4) upon the surface of layer 12, followed by a thermal anneal which results in the deposited metal forming a metallic alloy with the underlying semiconductor material. Alternatively, n-type dopants can be ion implanted into ohmic regions 56, followed by a metal deposition by evaporation, sputtering, or CVD, atop this region. Or the material in ohmic contact regions 56 can be etched away, n-type material can be regrown in this region by MOCVD or MBE, and metal can then be deposited atop this region. FIG. 8B shows a plan view of the device in FIG. 8A, where dashed line 80 indicates the cross section illustrated in FIG. 8A. As seen in FIG. 8B, alternating fingers of source contacts 14 and drain contacts 15 are deposited, such that the spacing between adjacent source and drain fingers is approximately the same throughout the device.

Next, as seen in FIG. 9, the additional dielectric layer 21 and electrode-defining layer 33 are deposited over passivation layer 22, for example by PECVD, sputtering, or evaporation. A recess is then etched through the electrode-defining layer, for example by reactive ion etching RIE or inductively coupled plasma (ICP) etching. The procedure for forming the recess is illustrated in FIGS. 10-16.

Referring to FIG. 10A, a photoresist masking layer 71 is patterned on the electrode-defining 33 to have an opening 72. Patterning can be performed by standard lithography procedures. FIG. 10B shows a plan view of the device in FIG. 10A, where dashed line 90 indicates the cross section illustrated in FIG. 10A. Source and drain fingers 14 and 15, which are covered by the photoresist masking layer 71, are indicated by rectangles with dashed lines. As seen in FIG. 10B, the opening 72 in the photoresist masking layer 71 is formed in a serpentine-like pattern with regions of width S1′ interlaced with regions of width D1′, where S1′ is approximately the same as width S1 in FIG. 6, and D1′ is approximately the same as width D1 in FIG. 6. The portions of the opening 72 that are directly between adjacent source and drain fingers are positioned substantially closer to the source fingers than to the drain fingers; hence, D1′ is substantially larger than S2′. Consequently, the volume and surface area of photoresist in the regions of width D1′ is substantially larger than that in the regions of width S1′.

The photoresist in the masking layer 71 is then redistributed, for example by thermally annealing the structure, resulting in the photoresist profile shown in FIG. 11. The anneal is performed at a temperature that does not damage the photoresist layer 71 or any of the underlying layers. As illustrated in FIG. 11, following the redistribution of the photoresist, the photoresist masking layer has slanted sidewalls 73 and 74. The exact slope and resulting profile of sidewalls 73 and 74 depends at least partially on the volume and/or surface area of the portion of photoresist directly adjacent to the sidewall. Because the portion of photoresist adjacent to sidewall 74 (which has a width D1′) has a substantially larger volume and surface area than the portion of photoresist adjacent to sidewall 73 (which has a width S1′), the resulting sidewall profile in opening 72 is asymmetric, with sidewall 73 being steeper than sidewall 74. The resulting profile of the photoresist layer 71 and the sidewalls 73 and 74 can be further controlled by varying anneal conditions, such as anneal time, anneal temperature, and the chemistry of the ambient gas in which the anneal is performed. For example, a longer anneal time or a higher temperature may result in a smaller slope in the sidewalls 73 and 74, although the asymmetry illustrated in FIG. 11 and described above still remains.

Referring to FIG. 12, the recess in the electrode-defining layer 33 is then partially formed by performing a first etch employing an etch chemistry that etches both the photoresist in layer 71 and the material of the electrode-defining layer 33. For example, if the electrode-defining layer 33 is SiN_(x), the first etch can be performed by Reactive Ion Etching (RIE) or Inductively Coupled Plasma (ICP) etching using an etch chemistry that includes O₂ and SF₆. In some implementations, the first etch is a substantially anisotropic etch.

As illustrated in FIG. 13, a second etch is then performed which etches the photoresist masking layer 71 without substantially etching the electrode-defining layer 33, thereby increasing the width of the opening 72. For example, if the electrode-defining layer 33 is SiN_(x), the second etch can be performed by Reactive Ion Etching (RIE) or Inductively Coupled Plasma (ICP) etching using an etch chemistry that includes only O₂. In some implementations, the second etch is a substantially isotropic etch. A third etch is then performed which, like the first etch, utilizes an etch chemistry that etches both the photoresist in layer 71 and the material of the electrode-defining layer 33, resulting in the profile of FIG. 14. As shown in FIG. 14, the horizontal width 74 of the sidewall being formed on the source side of the recess in the electrode-defining layer 33 is greater than the horizontal width 73 of the sidewall being formed on the source side of the recess. The photoresist etch procedure, followed by the procedure for etching both layers 71 and 33, are then repeated multiple times, until the recess 17 extends all the way through the electrode-defining layer 33, resulting in the aperture having a stepped sidewall. The photoresist masking layer 71 is then removed, for example by a solvent clean, resulting in the profile shown in FIG. 15. Additional dielectric layer 21 can be formed of a material that is not substantially etched by the etch procedure used to etch the recess in the electrode-defining layer 33. In such cases, the additional dielectric layer 21 functions as an etch stop layer.

Referring to FIG. 16, the portion of the additional dielectric layer 21 which is adjacent to the recess 17 in electrode-defining layer 33 is then removed, for example by performing an etch which etches the material of the additional dielectric layer 21 but does not etch the material of electrode-defining layer 33 or passivation layer 22. For example, when layers 33 and 22 are both SiN_(x), and layer 21 is AlN, the portion of layer 21 adjacent to the recess 17 in electrode-defining layer 33 can be chemically etched in a base, such as a photoresist developer. Finally, electrode 59 is deposited conformally in the recess, for example by evaporation, sputtering, or CVD, resulting in the transistor of FIG. 17, which is the same as the transistor of FIG. 4. To form the transistor of FIG. 5, prior to depositing the electrode 59, an additional etch is performed which extends the recess 17 through the passivation layer 22 and into the III-N material structure.

Due to the nature of the etch process described above for forming the recess 17 in electrode-defining layer 33, sidewalls 43 and 46 (labeled in FIG. 17) each have the same number of steps. Steps on opposite sidewalls which are formed simultaneously have substantially the same height. For example, referring to the device of FIG. 17, steps 81 and 91, which were formed simultaneously, have substantially the same height. Similarly, steps 82 and 92 have substantially the same height, steps 83 and 93 have substantially the same height, and steps 84 and 94 have substantially the same height. Furthermore the size and width of each of steps 81-84 is substantially proportional to the size and width of the corresponding step on the opposite sidewall. That is, the ratio of the width of step 81 to the width of step 91, the ratio of the width of step 82 to the width of step 92, the ratio of the width of step 83 to the width of step 93, and the ratio of the width of step 84 to the width of step 94 are all about the same, i.e., substantially the same. In an alternative process in which each of the steps is formed by its own lithography procedure, the above relationship between ratios of widths of corresponding steps typically cannot be maintained due to alignment tolerances (e.g., misalignment) inherent in the lithography procedures.

The devices of FIGS. 4-6 can alternatively be formed using slightly modified versions of the methods described above. For example, the source and drain contacts 14 and 15, respectively, can be formed after formation of the recess 17 in electrode-defining layer 33. Additionally, for the device of FIG. 6, the additional etch step performed to extend the recess 17 into the III-N material structure can include the following steps. Once the recess extends through the passivation layer 22 to the uppermost surface of the III-N materials, and prior to deposition of electrode 59, the structure can be etched using an etch chemistry that etches III-N materials at a higher etch rate than that of the materials used for electrode-defining layer 33 and passivation layer 22. For example, when electrode-defining layer 33 and passivation layer 22 are both SiN_(x), a Cl₂ RIE or ICP etch can be performed, resulting in the recess extending into the III-N material structure.

Referring again to the device of FIG. 17, each of the steps 81-84 and 91-94 includes two surfaces (although the steps could each include additional surfaces). One of the surfaces is horizontal (i.e., substantially parallel to the uppermost surface of the III-N material structure), while a second surface is a slanted surface, and is at an angle relative to the uppermost surface of the III-N material structure. The slanted angle of the slanted surface of each step results from the slanted sidewall of the photoresist masking layer 71 used in the fabrication process, as was illustrated in FIG. 11. As previously described, the slant in the sidewalls of the photoresist layer was caused by a redistribution procedure such as a thermal anneal. However, the slanted surface of the steps 81-84 and 91-94 could alternatively be replaced with a substantially vertical surface. If a substantially vertical surface is desired instead of the slanted surface, then the photoresist redistribution procedure can be omitted or altered to change the resulting photoresist profile.

Referring to the sidewall 43 of the recess 17 which defines the shape of the field plate 54 in the device of FIGS. 4 and 17, it has been found that by including a greater number/density of steps without changing any of the other device parameters, higher voltage operation could be reliably achieved. Additionally, if the number/density of steps is increased, it has been found that the device can operate with similar reliability to a device with a lower number/density of steps even if the gate-drain spacing (labeled L_(GD) in FIG. 17) is decreased, which is an unexpected result. Furthermore, if the number/density of steps is increased, it has been found that the device can operate with similar reliability to a device with a lower number/density of steps even if the field plate length (labeled L_(FP) in FIG. 17) is decreased, which is also an unexpected result. For example, devices having a field plate length L_(FP) equal to 11.5 microns (where L_(FP) is defined as the horizontal length from point 44 to the edge of the field plate, as illustrated in FIG. 17) and 8 steps (e.g., a step density greater than 0.4 steps per micron of field plate length), and a gate-drain spacing L_(GD) (where L_(GD) is defined as shown in FIG. 17) equal to 18 microns (e.g., less than 20 microns) were found to reliably support drain-source voltages of at least 600V when the device was in the off-state (i.e., when the gate was biased relative to the source at a voltage lower than the device threshold voltage). In these devices, the off-state drain current per unit gate width at 600V drain-source voltage with the gate biased below the device threshold voltage relative to the source was less than 10⁻⁸ Amps/mm, and the DC on-resistance was less than 16 ohm-millimeters, where the DC on-resistance is defined as the slope of DC current-voltage curve of the device at low drain-source voltages when the gate is biased on. By increasing the thickness of the metals used for the source and drain ohmic contacts, the DC on-resistance could be further reduced to about 12 ohm-millimeters or less. These devices also had very low DC-RF dispersion; the dynamic on-resistance of the device, defined as the on-resistance under switching conditions, was less than 1.1 times (e.g., substantially less than 1.5 times) the DC on-resistance for switching times (i.e., slew rates) of 2 microseconds or less. In comparison, devices formed with field plates having only 3 steps, but having an otherwise similar structure to the devices described above, required a gate-drain spacing L_(GD) of 22 microns (e.g., greater than 20 microns) to reliably support drain-source voltages of at least 600V when the devices was in the off-state. Furthermore, these devices exhibited substantially greater DC and dynamic on-resistances due to the increased gate-drain spacing.

Additionally, the relative sizes of step 81 and the steps closest to step 81 (steps 82-84) have also been found to affect the reliability of the devices during high voltage operation. Specifically, having step 82 and optionally step 83 be substantially smaller than step 81, followed by a larger step (step 84), as shown in FIG. 17, increases the reliability of the devices during high voltage operation. This too is an unexpected result. It is speculated that having such a step size pattern reduces the peak electric field near the drain-side edge of the intrinsic gate (i.e., near point 44) while still maintaining high fields along the remainder of the length of the field plate, thereby allowing for large voltages to be supported with a lower peak electric field.

As stated earlier, III-N layers 11 and 12 have different compositions from one another. The compositions are selected such that the second III-N layer 12 has a larger bandgap than the first III-N layer 11, which helps enable the formation of 2DEG 19. As an example, III-N layer 11 can be GaN and III-N layer 12 can be AlGaN or AlInGaN or BAlInGaN, whereas layer 12 can be n-doped or can contain no significant concentration of doping impurities. In the case that layer 12 is undoped, the induced 2DEG results from the difference in polarization fields between layers 11 and 12.

If III-N layers 11 and 12 are composed of III-N material oriented in a non-polar or semi-polar orientation, then doping all or part of the second semiconductor layer 12 with an n-type impurity may also be required to induce the 2DEG 19. If the III-N layers 11 and 12 are oriented in a polar direction, such as the [0 0 0 1] (i.e., group III-face) orientation, then 2DEG 19 may be induced by the polarization fields without the need for any substantial doping of either of the III-N layers, although the 2DEG sheet charge concentration can be increased by doping all or part of the second III-N layer 12 with an n-type impurity. Increased 2DEG sheet charge concentrations can be beneficial in that they can reduce the diode on-resistance, but they can also lead to lower reverse breakdown voltages. Hence the 2DEG sheet charge concentration preferably is optimized to a suitable value for the application in which the diode is used.

Substrate 10 can be any suitable substrate upon which III-N layers 11 and 12 can be formed, for example silicon carbide (SiC), silicon, sapphire, GaN, AlN, or any other suitable substrate upon which III-N devices can be formed. In some implementations, a III-N buffer layer (not shown) such as AlGaN or AlN is included between substrate 10 and semiconductor layer 11 to minimize material defects in layers 11 and 12.

FIG. 18 shows a cross-sectional view of a III-N HEMT transistor similar to the device of FIGS. 4 and 17, but which is fabricated on III-N semiconductor material that is either oriented in the N-polar [0 0 0 1 bar] direction or is a nitrogen-terminated semipolar material. The device includes a substrate 200 which is suitable for growth of N-polar or semipolar III-N materials. Layer 201 is a buffer layer, such as GaN or AlN, which reduces the defect density in the overlying III-N material. In some cases, it is possible to omit layer 201 and grow III-N layer 204 directly on the substrate 200. The composition of III-N layers 204 and 202 are chosen such that a 2DEG 19 can be induced in layer 202 near the interface between layers 202 and 204. For example, layer 204 can be AlGaN or AlInGaN, and layer 202 can be GaN. An additional III-N layer (not shown), such as a layer of AlN, can be included between III-N layers 204 and 202. Another additional III-N layer (not shown) such as AlInGaN, AlInN, or AlGaN, may also be included on an opposite side of III-N layer 202 from III-N layer 204. Electrode-defining layer 33, which again includes a recess, is similar to or the same as that of FIGS. 4 and 17. A gate 59 is formed in the recess. The gate 59 includes an active gate portion 61 in gate region 51 of the device, as well as extending portions 54 and 55, as in FIGS. 4 and 17. The gate 59 is deposited conformally in the recess in the electrode-defining region with extending portion 54 over a sidewall 43 of the recess. Hence, the profile of extending portion 54 is at least partially determined by the profile of the sidewall 43. Source and drain contacts 14 and 15, respectively, are on opposite sides of the gate 59 and form ohmic contacts to the 2DEG channel 19.

As in the HEMT of FIGS. 4 and 17, a passivation layer 22, such as a layer of SiN_(x), can be included on the uppermost surface of the III-N material structure, and an additional dielectric layer 21, such as a layer of AlN, can be included between the electrode-defining layer 33 and the passivation layer 22. As shown in FIG. 18, the recess in the electrode-defining layer 33 can extend through the entire thickness of the additional dielectric layer 21 but not through the passivation layer 22, such that passivation layer 22 also serves as a gate insulator.

The III-N HEMT of FIG. 18 can be an enhancement-mode (i.e., normally off, with a threshold voltage greater than 0V) or a depletion-mode (i.e., normally on, with a threshold voltage less than 0V) device. Other configurations for the III-N HEMT of FIG. 18 are also possible. For example, in one implementation, the recess in the electrode-defining layer 33 only extends partially through the thickness of the electrode-defining layer 33, such that a portion of the electrode-defining layer 33 is between the III-N materials and gate portion 61 (not shown). In this case, electrode-defining layer 33 can also function as a gate insulator, and it may be possible to omit the passivation layer 22 and/or the additional dielectric layer 21. In another implementation, the recess in the electrode-defining layer 33 additionally extends through the entire thickness of the passivation layer 22, and the gate 59 directly contacts the underlying III-N material (not shown). In yet another implementation, the recess further extends into the III-N materials (not shown), such as through the 2DEG 19, as in the transistor of FIG. 5.

The procedures for forming the device of FIG. 18 are the same as the procedures shown in FIGS. 7-16 for forming the device of FIG. 4, with the exception that the III-N layers formed on the substrate in FIG. 18 have a different crystallographic orientation as compared to the III-N layers formed on the substrate in FIG. 4.

A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the techniques and devices described herein. Features shown in each of the implementations may be used independently or in combination with one another. Accordingly, other implementations are within the scope of the following claims. 

What is claimed is:
 1. A III-N transistor, comprising: a III-N material structure; a source and a drain; an electrode-defining layer having a thickness, the electrode-defining layer being over a surface of the III-N material structure, the electrode-defining layer having a recess with a first sidewall proximal to the drain and a second sidewall proximal to the source, the first and second sidewalls each comprising a plurality of steps; and an electrode in the recess, the electrode including an extending portion at least partially over the first sidewall; wherein the first sidewall forms a first effective angle relative to the surface of the III-N material structure and the second sidewall forms a second effective angle relative to the surface of the III-N material structure, the second effective angle being larger than the first effective angle; the electrode includes a gate in a gate region of the transistor; the plurality of steps in the first and second sidewalls each include a first step having a first step width directly adjacent to the gate, a second step having a second step width directly adjacent to the first step, and a third step having a third step width directly adjacent to the second step; a ratio of the first step width to the second step width in the plurality of steps in the first sidewall is substantially the same as a ratio of the first step width to the second step width in the plurality of steps in the second sidewalk; and a sum of the first step width, the second step width, and the third step width in the first sidewall is greater than a sum of the first step width, the second step width, and the third step width in the second sidewall.
 2. The transistor of claim 1, wherein the second effective angle is substantially larger than the first effective angle.
 3. The transistor of claim 1, wherein the second effective angle is at least 10 degrees larger than the first effective angle.
 4. The transistor of claim 1, wherein the III-N material structure comprises a first III-N material layer, a second III-N material layer, and a 2DEG channel induced in the first III-N material layer adjacent to the second III-N material layer as a result of a compositional difference between the first III-N material layer and the second III-N material layer.
 5. The transistor of claim 4, wherein the first III-N material layer includes GaN and the second III-N material layer includes AlGaN, AlInN, AlInGaN, or BAlInGaN.
 6. The transistor of claim 4, wherein the first III-N material layer and the second III-N material layer are group III-face or [0 0 0 1] oriented or group-III terminated semipolar layers, and the second III-N material layer is between the first III-N material layer and the electrode-defining layer.
 7. The transistor of claim 4, wherein the first III-N material layer and the second III-N material layer are N-face or [0 0 0 0−1] oriented or nitrogen-terminated semipolar layers, and the first III-N material layer is between the second III-N material layer and the electrode-defining layer.
 8. The transistor of claim 4, wherein the recess extends through the entire thickness of the electrode-defining layer.
 9. The transistor of claim 8, wherein the recess extends into the III-N material structure.
 10. The transistor of claim 9, wherein the recess extends through the 2DEG channel.
 11. The transistor of claim 1, wherein the electrode-defining layer comprises SiN_(x).
 12. The transistor of claim 1, wherein a thickness of the electrode-defining layer is between about 0.1 microns and 5 microns.
 13. The transistor of claim 1, further comprising a dielectric passivation layer between the III-N material structure and the electrode-defining layer, the dielectric passivation layer directly contacting a surface of the III-N material adjacent to the electrode.
 14. The transistor of claim 13, wherein the dielectric passivation layer comprises SiN_(x).
 15. The transistor of claim 14, wherein the dielectric passivation layer is between the electrode and the III-N material structure, such that the electrode does not directly contact the III-N material structure.
 16. The transistor of claim 14, further comprising an additional insulating layer between the dielectric passivation layer and the electrode-defining layer.
 17. The transistor of claim 16, wherein the additional insulating layer comprises AlN.
 18. The transistor of claim 1, wherein the extending portion of the electrode directly contacts the first sidewall.
 19. The transistor of claim 1, wherein a ratio of the first step width to the third step width in the plurality of steps in the first sidewall is substantially the same as a ratio of the first step width to the third step width in the plurality of steps in the second sidewall.
 20. A III-N transistor, comprising: a III-N material structure; an electrode-defining layer having a thickness, the electrode-defining layer being over a surface of the III-N material structure, the electrode-defining layer having a recess with a first sidewall proximal to a drain of the III-N transistor and a second sidewall opposite the first sidewall, the first and second sidewalls each comprising a plurality of steps; and an electrode in the recess, the electrode including an extending portion at least partially over the first sidewall; wherein the plurality of steps in the first and second sidewalls each include a first step having a first step width directly adjacent to the gate, a second step having a second step width directly adjacent to the first step, and a third step having a third step width directly adjacent to the second step; and a sum of the first step width, the second step width, and the third step width in the first sidewall is greater than a sum of the first step width, the second step width, and the third step width in the second sidewall.
 21. The transistor of claim 20, wherein a ratio of the first step width to the second step width in the plurality of steps in the first sidewall is substantially the same as a ratio of the first step width to the second step width in the plurality of steps in the second sidewall. 